This invention generally relates to electronic systems and in particular it relates to low voltage to high voltage level shifters.
The design of a low voltage to high voltage level shifter usually involves striking a balance between the strength of the pull-down NMOS transistors 20 and 22 and the cross gate-connected PMOS transistors 24 and 26 as shown in the prior art circuit of FIG. 1. The circuit of FIG. 1 also includes inverters 28 and 30; input IN; low voltage source VL; high voltage source VH; outputs OUT and OUT_B; and ground node gnd. If the gains of the NMOS transistors 20 and 22, and PMOS transistors 24 and 26 are similar, there is the risk of the level shifter not switching output states. If the NMOS transistors 20 and 22 are much stronger than the PMOS transistors 24 and 26, then the propagation delay of the rising edge of the outputs OUT and OUT_B can be much longer than in the falling edge, due to the weak PMOS transistors. This can be a problem in certain applications, when both rising and falling propagation delays are significant factors.
A low voltage to high voltage level shifter has falling-edge 1-shot circuits coupled to the outputs of a basic level shifter with cross gate-connected transistors and two pull-down transistors. The falling-edge 1-shot circuits output a narrow pulse when these outputs transition from a high state to a low state. These pulses are used to set and reset a flip-flop. The flip flop provides an output that is only dependent on the very fast fall times of the outputs of the basic level shifter. This allows the level shifter to be designed for optimal transitional performance without the sacrifice of a potentially long propagation delay on the output nodes.